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1 spmic for micro converter bias and drivers ISL1801 the ISL1801 is a power management ic (pmic) optimized for solar array micro converters and other systems operating from a high voltage dc supply. the ISL1801 can be used in buck, boost or buck-boost microconverter topologies in order to maximize the energy harvest from a solar array. in addition to the power stage and main controller, the ISL1801 includes the bias regulators, gate drivers, current sense amplifier and comparators needed for micro converters. the ISL1801 integrates two switching regulators that can be used to generate the driver and the micro-controller (mcu) power supplies. in addition, it has a low offset, low drift amplifier for current sensing, two comparators for overvoltage and overcurrent protection plus a watchdog timer to reset the mcu if necessary. this single ic solution offers high integration and dramatically reduces the to tal number of components in the microconverter system improv ing the system reliability and reducing cost. the first regulator takes input voltages ranging from 9v to 90v from the solar panel and outputs a regulated supply for drivers and the secondary regulator. the secondary regulator converts the output of the first regulator to a programmable micro-controller supply, typically 3.3v. a high voltage start-up ldo provides the necessary bias voltage until the switching regulator is operating. the ISL1801 integrates two high-speed mosfet drivers for buck, flyback or boost converters configured as shown in the application schematics. the driv e3 also has the integrated peak current limiting capabilities. the ISL1801 includes comprehe nsive start-up, shutdown and fault logic to ensure reliable operation of micro converters in solar applications. features ? 90v input buck switching regulator - 120ma (minimum) output with ocp, ovp, otp - integrated upper and lower mosfets ? 90v on-chip start-up 6.7v ldo ? low voltage buck switching regulator - 200ma (minimum) output with ocp, ovp - integrated upper and lower mosfets -pgood output ? low voltage bias ldo - input voltage range from 6v to 14v - regulated 5v output up to 10ma ? dual high-speed gate driver -14v voltage rating - 2a peak sourcing and 5a peak sinking current - peak current limit for drive3 ? dedicated amplifier for accurate current sense ? two comparators for general purpose protection ? integrated watchdog timer applications ?solar power optimizer ? solar power micro-inverter ? solar charge controller ? telecom power supply figure 1. typical application pv module ISL1801 processor and/or communications v out - v out + v in + 3.3v sense control july 24, 2014 fn8259.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2012, 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL1801 2 fn8259.1 july 24, 2014 submit document feedback table of contents block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 high voltage 10v bias regulator vr1 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 low voltage 3.3v bias regulator vr2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 driver electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 watchdog timer electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 current sense op amp electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 dual high-speed comparator electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 preload electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 summary of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 dual synchronous buck switching regulators with constant on time control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 dual ldo bias supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 dual low-side mosfet drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 dual high-speed comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 precision amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 preload operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 over-temperature protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 pc board layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 layout procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ISL1801 3 fn8259.1 july 24, 2014 submit document feedback block diagram figure 2. ISL1801 block diagram vcc5v vin1 ldo2 fb1 pwm1 ton1 wdo pgood2 boot1 phase1 vcc5v vin2 phase2 amp- amp+ ampo pgnd1 pgnd2 wdi vcc1 + - sgnd gnd uvlo pwm logic pwm logic en1 oc, ov, ot, ss on-time control vcc5v boot2 level shift agnd ldo1 timer preload gnd gnd pvcc3 pre-load control watchdog ss, oc, ov, ot vddref pvcc3 pwm3 rpwm3 cmp1o cmp1- cmp1+ cmp2- cmp2 cmp1 latchrpt pgnd3 drive3 cmp2+ gnd + - 7v pvcc3 q q set clr s r phase3 pvcc3 pgnd4 bdrive ocset3 pvcc3 cl breset bcmd q q set clr s r + - 0.5*vddref one shot enable enable 120a q q set clr s r + - vref1 vcc1 ton2 isen + - fb2 + - vref2*0.88 vref2 delay gnd q q set clr s r vddref on-time control por q q set clr s r ff1 ff2 ff3
ISL1801 4 fn8259.1 july 24, 2014 submit document feedback pin configuration ISL1801 (48 ld tssop) top view pin descriptions pin# pin name description 1, 2, 6, 44, 46, 48 nc1, nc2, nc3, nc4, nc5, nc6 nc pin. 3 vcc1 high voltage start-up ldo1 output and also the pin providin g bias to the hv circuitry on the ISL1801. place a 1f ceramic capacitor from this pin to ground as deco upling cap. connect this pin to the output of the high voltage regulator. when the output of the switching regulator is stable, the start-up ldo is disabled and the chip bias is supplied by the more efficient switching regulator. note: as vcc1 is the power supply of the high voltage die, do not connect it to any low impedance potential by any means. this may damage the device. 4 agnd analog ground pin for vcc1. 5 ocset3 a resistor between this pin and ground set the peak curr ent limit threshold for the power stage mosfet at phase3. the 0. 01f capacitor can be used at this pi n to filter any switching noise. 7 phase3 the phase node pin of the power stage controlled by drive3 . this pin should be connected to the drain of the power mosfe t through one resistor and diode which prevent the voltage at ph ase3 pin from dropping below -0.6v. refer to the typical application schematics starting on page 24, for correct connections. 8 pgnd3 the ground pin for the high-speed driver drive3. 9 drive3 the output of the high-speed driver. 10 pvcc3 the bias input pin for both the high-speed driver and the low speed driver. it is normally connected to v out1 . the pvcc3 also powers ldo2 which provides the bias supply for all internal control circuits. 11 bdrive the output of the high-speed dr iver controlled by the bcmd signal. 12 pgnd4 the ground pin for bdrive. 13 pwm3 the pwm input signal for drive3. nc1 1 nc2 2 vcc1 3 agnd 4 ocset3 5 nc3 6 phase3 7 drive3 8 pvcc3 9 bdrive 10 pgnd4 11 pwm3 12 rpwm3 13 bcmd 14 wdi 15 vddref 16 latchrpt 17 pgood2 18 ampo 19 20 amp- 21 amp+ 22 23 24 nc6 48 pgnd1 47 46 45 nc5 44 vin1 43 nc4 42 phase1 41 boot1 40 ton1 39 fb1 38 preload 37 gnd 36 vin2 35 boot2 34 phase2 33 pgnd2 32 ton2 31 30 cmp1o 29 28 cmp2- 27 cmp1- 26 cmp1+ 25 breset timer cmp2+ pgnd3 sgnd vcc5v fb2
ISL1801 5 fn8259.1 july 24, 2014 submit document feedback 14 rpwm3 the reset signal for both flip-flops in the latchrpt ci rcuit and overcurrent-protection circuit of drive3/phase3. the rpwm3=0 will reset both flip-flops. avoid running pwm3=1 with rpwm3=0 for a long time or at very high frequency, since it may result in very high switching frequency at drive3 in the overcurrent protection condition. 15 bcmd logic input to control bdrive. 16 breset logic input to reset the latchrpt flip-flop in the bdri ve control circuit. 17 wdi watchdog circuit clock input signal. 18 vddref reference signal for output signals to the mcu. connect this pin to v out2 , which provides a clamp voltage for all the output pins (cmp1o, ampo) interfacing with the mcu. 19 latchrpt open drain output signal. when either comparator or ph ase3 overcurrent protection is triggered, this pin is pulled lo w to inform the mcu. the two internal flip-flops used to latch these faults can be reset by setting rwpm3=0. 20 pgood2 open drain output pin indicating power-good for the low vo ltage regulator. a logic low signal at the watchdog output wi ll also pull this pin low allowing it to reset the mcu in either fault condition. 21 ampo integrated amplifier output. 22 amp- integrated amplifier inverting input. 23 amp+ integrated amplifier non-inverting input. 24 sgnd the ground pin of the sensitive contro l circuits biased by vcc5v. connect this pin to a ground plane with minimum noise. 25 cmp1+ comparator 1 non-inverting input. 26 cmp1- comparator 1 inverting input. 27 cmp1o comparator 1 output. this signal also tr iggers the flip-flop for the latchrpt signal. 28 cmp2- comparator 2 inverting input. 29 cmp2+ comparator 2 non-inverting input. 30 fb2 the feedback sense pin for the low voltage switching regula tor. the output voltage is programmable by a resistor divider feeding back the output voltage. 31 ton2 on time adjustment for the secondary (low voltage) switching regulator. connect a resistor from this pin to the input vol tage of the low voltage regulator to adjust the on time and switching frequency. 32 pgnd2 the ground pin of the low voltage switching regulator?s po wer stage. there are switching power current pulses coming out of this pin. place the ground pad of the input power stage decoupling cap as close to this pin as possible. 33 phase2 the phase node of the low voltage switching regulato r. this pin should be connected to the output inductor. 34 boot2 the boot pin of the low voltage switching regulator. an external bootstrap capacitor is required. this pin provides bias voltage to the high-side mosfet driver. a bootstrap circuit is used to create a voltage suitable to dr ive the internal n-channel mosfet . the boot diode is included within the ic. 35 vin2 input of the low voltage switching regulator. this pin is connected to the drain of the internal high-side mosfet. 36 vcc5v the output of the internal 5v ldo providing the bias su pply for the ic. a 1f ceramic deco upling capacitor should be pla ced from this pin to ground. 37 gnd the analog ground pin. 38 preload place a resistor from this pin to v out1 to provide the loading for the high voltage switching regulator. when this load can be successfully driven, the low voltage switching regulator will be en abled. if the pv module output power is insufficient, the lo w voltage switching regulator will not start. 39 fb1 the feedback sense pin for the high voltage switching regula tor. the output voltage is programmable by a resistor divider feeding back the output voltage. 40 ton1 on time adjustment for the high voltage switching regulator. connect a resistor from this pin to the input voltage of the high voltage regulator to adjust the on time and switching frequency. 41 timer tie a resistor from vcc5v to this pi n and a cap from this pin to ground. the rc time constant sets the time needed for b oth start-up and watchdog timing. a minimum of 0.01f should be co nnected to this pin to filter the switching noise from boot1. the pull-up resistor shou ld not be more than 200k to assure correct operation. pin descriptions (continued) pin# pin name description
ISL1801 6 fn8259.1 july 24, 2014 submit document feedback 42 boot1 the boot pin of the high voltage switching regulator. an external bootstrap capacitor is required. this pin provides bia s voltage to the high-side mosfet driver. a bootstrap circuit is used to create a voltage suitable to dr ive the internal n-channel mosfet . the boot diode is included within the ic. 43 phase1 the phase node of the high voltage switching regulator, vr1. this pin should be connected to the output inductor. 45 vin1 input to both the high voltage switching regulator and the high voltage start-up ldo1. this pin connects the high voltage supply to the drain of the internal high-side mosfet. 47 pgnd1 the ground pin of the high voltage switching regulator?s power stage. there are switching power current pulses coming ou t of this pin. place the vin1 decoupling capacitor as close as possible to this pin. ordering information part number ( notes 1 , 2 , 3 ) part marking v in1 range (v) temp range (c) package (pb-free) pkg. dwg. # ISL1801ivz ISL1801 ivz 9 to 90 -40 to +85 48 ld tssop m48.240 ISL1801eval1za evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operation s). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL1801 . for more information on msl please see tech brief tb363 . pin descriptions (continued) pin# pin name description
ISL1801 7 fn8259.1 july 24, 2014 submit document feedback absolute maximum rating s thermal information supply voltage, vcc1, vboot1-vphase1 . . . . . . . . . . . . . . . . . -0.3v to 16v voltage on vin1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 100v voltage on boot1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 116v voltage on phase1, phase3 . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 100v voltage on vin2, preload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 16v voltage on phase2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 16v voltage on boot2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 22.5v bdrive, drive3 voltages . . . . . . . . . . . . . . . . . . . . . . -0.3v to pvcc3 +0.3v supply voltage, vcc5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v voltage on all other pins . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc5v +0.3v ldo(vcc5v) current (continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma ldo(vcc1) current (continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 200v latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 48 ld tssop package ( notes 4 , 5 ) . . . . . . 58 16 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage, vcc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v to 14v voltage on vin1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9v to 90v voltage on boot1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15v to 104v voltage on vin2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v to 14v voltage on boot2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10.5v to 19.5v supply voltage, vcc5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 5.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for ? jc , the ?case temp? location is taken at the package top center. high voltage 10v bias regulator vr1 electrical specifications t a = +25c, vr1 = 10v, vr2 = 3.3v. boldface limits apply across the operating temperature range, -40c to +85c. ( notes 6 , 7 ) symbol parameter test conditions min ( note 7 ) typ ( note 6 ) max ( note 7 )units v in1 supply v in1 input voltage range 9 90 v shut-down current v in1 = 9v to 90v 700 1000 a operating current v in1 = 9v to 90v, pvcc3 = 0v, all inner circuits of the low voltage section are disabled, and only ldo1 and some inner circuits of the high voltage section are running. 1.3 2 ma vcc1 supply vcc1 ldo regulator output 6.8 v rising uv threshold 5.2 5.9 6.6 v uv threshold hysteresis 1v reference and soft-start v fb1 internal reference voltage 1.960 2.000 2.040 v power mosfets r ds(on) upper switch on-resistance i out = 50ma, boot1-phase1 = 6v, test at wafer sort 2.3 3.2 r ds(on) lower switch on-resistance i out = 50ma, vcc1 = 10v, test at wafer sort 1.2 2 on time generator t on v in1 = 10v, r on = 1m 2.75 3 3.25 s t on v in1 = 90v, r on = 1m 0.3 s minimum off time t minoff 0.3 s
ISL1801 8 fn8259.1 july 24, 2014 submit document feedback minimum on time t minon 0.3 s regulation and ripple output voltage ripple v in1 = 40v, v out = 10v, f sw = 100khz, l out = 470h, c out = 22f 100 mv overcurrent protection overcurrent protection threshold test on wafer sort and characterized on bench 120 185 250 ma overvoltage protection fb1 ovp threshold 2.4 v thermal shutdown thermal shut-down temperature rising threshold 150 c thermal shut-down hysteresis 30 c high voltage 10v bias regulator vr1 electrical specifications t a = +25c, vr1 = 10v, vr2 = 3.3v. boldface limits apply across the operating temperature range, -40c to +85c. ( notes 6 , 7 ) (continued) symbol parameter test conditions min ( note 7 ) typ ( note 6 ) max ( note 7 )units low voltage 3.3v bias regulator vr2 electrical specifications t a = +25c, vr1 = 10v, vr2 = 3.3v. boldface limits apply over the operating temperature range, -40c to +85c. ( notes 6 , 7 ) symbol parameter test conditions min ( note 7 ) typ ( note 6 ) max ( note 7 )units v in2 supply input voltage range 14 v vcc5 supply vcc5 ldo output 5v rising uv threshold 4.760 5.000 5.190 v hysteresis 165 mv reference and soft-start v fb2 internal reference voltage 0.686 0.700 0.714 v soft-start interval current limiting threshold of vr2 ramps from 25% to 100% 1.5 ms power mosfets r ds(on) upper switch on-resistance i out = 200ma 1 2 r ds(on) lower switch on-resistance i out = 200ma 1 2 on time generator (4 trim options) t on v in2 = 10v, r on = 1m 950 1100 1250 ns t on v in2 = 12v, r on = 1m 800 ns minimum on time t minon 150 ns minimum off time t minoff 150 ns regulation and ripple output voltage ripple v in2 = 10v, v out2 = 3.3v, f sw = 300khz, l out = 47h, c out = 22f 30 mv
ISL1801 9 fn8259.1 july 24, 2014 submit document feedback overcurrent protection overcurrent protection threshold 200 245 300 ma overvoltage protection fb2 ovp threshold 0.775 v pgood2 (open drain output) power-good lower threshold fraction of v out2 set point; 3s noise filter 83 90 95 % pgood2 leakage current v pullup = 3.3v 1 a pgood2 voltage low i pgood2 = 4ma 0.5 v low voltage 3.3v bias regulator vr2 electrical specifications t a = +25c, vr1 = 10v, vr2 = 3.3v. boldface limits apply over the operating temperature range, -40c to +85c. ( notes 6 , 7 ) symbol parameter test conditions min ( note 7 ) typ ( note 6 ) max ( note 7 )units driver electrical specifications t a = +25c, vr1 = 10v, vr2 = 3.3v. boldface limits apply over the operating temperature range, -40c to +85c. ( notes 6 , 7 ) symbol parameter test conditions min ( note 7 ) typ ( note 6 ) max ( note 7 )units pvcc3 supply shutdown current pvcc3 = 3v 0.85 1.1 ma operating current pvcc3 = 10v, drive3 = bdrive = 1, or 0 1.75 3.2 ma operating current pvcc3 = 10v, f s = 50khz, 10nf load on drive3 8 11 ma logic input pins low level voltage threshold pwm3, rpwm3, bcmd, breset, vddrfe = 3.3v 0.7 v high level voltage threshold pwm3, rpwm3, bcmd, breset, vddrfe = 3.3v 2.4 v hysteresis 187 mv input pull-down current 500 na drive3 and bdrive gate driver low level output voltage i drive = 100ma 50 250 mv high level output voltage i drive = -100ma 9.25 9.8 v peak pull-down current v drive = 0v 5 a peak pull-up current v drive = 10v 2 a active pull-down resistance before por vcc1 = 10v 270 600 overcurrent protection ocset3 oc threshold current current from ocset3 pin 110 120 130 a oc comparator input offset 3mv drive3 and bdrive switching characteristics t phl turn-off propagation delay pwm falling to drive falling 200 320 ns t plh turn-on propagation delay pw m rising to drive rising 150 300 ns t rc output rise time (10% to 90%) c l = 10nf 90 ns t fc output fall time (90% to 10%) c l = 10nf 50 ns t pw input pulse width that changes the output 300 ns
ISL1801 10 fn8259.1 july 24, 2014 submit document feedback watchdog timer electrical specifications t a = +25c, vr1 = 10v, vr2 = 3.3v. boldface limits apply over the operating temperature range, -40c to +85c. ( notes 6 , 7 ) symbol parameter test conditions min ( note 7 ) typ ( note 6 ) max ( note 7 )units input pin wdi rising threshold wdi, vddrfe = 3.3v, vcc5 = 5v 1.50 1.64 1.80 v wdi falling threshold wdi, vddrfe = 3.3v, vcc5 = 5v 1.40 1.56 1.70 v wdi hysteresis 80 disable mode input voltage threshol d wdi, vddrfe = 3.3v, vcc5 = 5v 4.5 v inner pull-up resistor pull up to vcc5 37 50 61 k minimum pulse width wdi, vddrfe = 3.3v, vcc5 = 5v 300 ns time-out characteristics timer rising threshold vcc5 = 5v 4.5 v switching characteristics timer reset pulse width 1.5 ms timer leakage current timer = 5v 1.2 a timer voltage low i timer = 4ma 0.5 v pgood2 reset pulse width 1ms current sense op amp electrical specifications t a = +25c, vr1 = 10v, vr2 = 3.3v. boldface limits apply over the operating temperature range, -40c to +85c. ( notes 6 , 7 ) symbol parameter test conditions min ( note 7 typ ( note 6 ) max ( note 7 )units input offset voltage -1000 v input bias current 3na input offset current 1 na v cm_min minimum common-mode voltage -0.1 v v cm_max maximum common-mode voltage 2 v cmrr common-mode rejection ratio v cm = -0.1v to 2v 100 db psrr power supply rejection ratio v cc = 3.3v to 5.5v, v out2 = 3.3v 100 db large signal voltage gain 220 v/mv maximum output voltage swing output low, r l = 100k to v cm 5.3 mv output high, r l = 100k to v cm ; vddref tied to 3.3v v out2 3.0 v short-circuit output source current r l = 10 to v cm 30 ma ac specifications gain bandwidth product r l = 10k to v cm 130 khz input noise voltage peak-to-peak f = 0.1hz to 10hz 1.4 v p-p input noise voltage density f o = 1khz 64 nv/ hz input noise current density f o = 10khz 0.19 pa/ hz slew rate 100 v/ms
ISL1801 11 fn8259.1 july 24, 2014 submit document feedback dual high-speed comparator electrical specifications t a = +25c, vr1 = 10v, vr2 = 3.3v. boldface limits apply over the operating temperature range, -40c to +85c. ( notes 6 , 7 ) symbol parameter test conditions min ( note 7 ) typ ( note 6 ) max ( note 7 )units input offset voltage -5.5 0 5.5 mv input bias current 1 pa input offset current 1 pa v cm_min minimum common-mode voltage -0.2 v v cm_max maximum common-mode voltage 3.3 v cmrr common-mode rejection ratio v cm = -0.2v to v out2 62 db input common-mode capacitance 2 pf input differential capacitance 4 pf output high voltage i out = -0.3ma; vddref tied to 3.3v v out2 2.7 3 v output low voltage i out = 0.3ma 175 300 mv short circuit current 1ma switching specifications low-to-high propagation delay time input overdrive = 100mv 0.55 s high-to-low propagation delay time input overdrive = 100mv 0.2 s cmp1 rise time cl = 10pf, cmp1+ toggled from 0v to 1v 5 100 550 ns cmp1 fall time cl = 10pf, cmp1+ toggled from 1v to 0v 5 100 550 ns latchrpt (open drain output) latchrpt one-shot pulse width und er pulse by pulse oc condition, latchrpt pulled low for one-shot period of each oc cycle 1.1 2.5 s latchrpt leakage current v pullup = 3.3v 1 a latchrpt voltage low i latchrpt = 4ma 0.5 v preload electrical specifications t a = +25c, vr1 = 10v, vr2 = 3.3v. boldface limits apply over the operating temperature range, -40c to +85c. ( notes 6 , 7 ) symbol parameter test conditions min ( note 7 typ ( note 6 ) max ( note 7 )units power mosfet r ds(on) switch 1 on on-resistance pull-up to vcc1 = 10v through 100 resistor ( note 8 ) 242 350 472 r ds(on) switch 2 on on-resistance pull-up to vcc1 = 10v through 100 resistor ( note 8 ) 90 120 165 r ds(on) switch 3 on on-resistance pull-up to vcc1 = 10v through 100 resistor ( note 8 ) 40 56 76 r ds(on) switch 4 on on-resistance pull-up to vcc1 = 10v through 100 resistor ( note 8 ) 8.7 11.4 14.8 notes: 6. compliance to datasheet values is assured by one or more methods: production test, characterization and/or design. 7. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. 8. not production tested.
ISL1801 12 fn8259.1 july 24, 2014 submit document feedback typical performance curves figure 3. vr1 efficiency vs load current with v out1 = 10v at f sw1 = 170khz figure 4. vr2 efficiency vs load current with v out2 =2.5vat f sw2 = 210khz figure 5. vr1 + vr2 effici ency vs input voltage figure 6. vr1 regulation vs load current with v out1 =10v at f sw1 = 170khz figure 7. vr2 regulation vs load current with v out2 = 2.5v at f sw2 = 210khz figure 8. vr1 switching frequency vs load current with v out1 = 10v 60 65 70 75 80 85 90 95 0 0.05 0.10 0.15 output current (a) efficiency (%) 45v in 60v in 75v in 15v in 30v in 90v in 80 82 84 86 88 90 92 94 0.025 0.075 0.125 0.175 0.225 output current (a) 10v in 6v in 14v in efficiency (%) 75 77 79 81 83 85 87 89 10 20 30 40 50 60 70 80 90 100 input voltage (v) efficiency (%) v out1 = 10v i out1 = 100ma f sw1 = 170khz v out2 = 2.5v f sw2 = 210khz i out2 = 200ma 9.98 10.00 10.02 10.04 10.06 10.08 10.10 10.12 10.14 00.050.100.15 v o u t 1 ( v ) output current (a) 45v in 60v in 75v in 90v in 15v in 30v in 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 2.56 0.025 0.075 0.125 0.175 0.225 v o u t 2 ( v ) output current (a) 10v in 6v in 14v in 120 130 140 150 160 170 180 190 00.050.100.15 f s w 1 ( k h z ) output current (a) 15v in 90v in 50v in
ISL1801 13 fn8259.1 july 24, 2014 submit document feedback figure 9. vr2 switching freque ncy vs load current with v out2 = 2.5v typical performance curves (continued) 50 70 90 110 130 150 170 190 210 230 250 0 0.05 0.10 0.15 0.2 f s w 2 ( k h z ) output current (a) 6v in 14v in 10v in
ISL1801 14 fn8259.1 july 24, 2014 submit document feedback test waveforms figure 10. vr1 soft-start (from top to bottom: phase1, i_l1, v out1 ) figure 11. vr2 soft-start with 200ma load (from top to bottom: phase2, i_l2, v out2 ) figure 12. watchdog operation fig ure 13. normal power-up sequence figure 14. soft-start when preload test fails figure 15. normal power-down sequence 200ma load holds v out2 at 0v until the inductor current is greater than 200ma the capacitor on the timer pin is 1nf to generate a very short preload duration for this plot
ISL1801 15 fn8259.1 july 24, 2014 submit document feedback figure 16. ocset3 threshol d crossing triggers ocp test waveforms (continued)
ISL1801 16 fn8259.1 july 24, 2014 submit document feedback summary of operation the ISL1801 is a versatile solar power management ic (spmic). it has two switching regulators, two ldos, two general purpose comparators, two power mosfet drivers, a current sense opamp and other logic functions. figure 17 shows the main blocks in the ISL1801. the high voltage ldo1 can be directly connected to a high voltage input power source up to 90v. the output can be used to start-up the high voltage switchin g regulator vr1. once the vr1?s output is greater than 6.7v, ldo1 is disabled to save power. the second low voltage regulator, ldo2, can be connected to the output of vr1 to generate the 5v supply required for the internal control circuits including th ose that operate vr1 and vr2. the first switching regulator, vr1, can be directly connected to an input voltage up to 90v. the vr1 provides a regulated voltage for the second switching regulator, vr2, and the two integrated mosfet drivers. the low voltage switching regulator, the vr2, can be used to generate the regulated voltage for an mcu or other external circuitry. the pgood2 signal is used to indicate that vr2 output voltage is within the regulation window. the output voltage of both vr1 and vr2 can be set through resistor dividers at the fb1 and fb2 pins respectively. the switching frequencies of vr1 and vr2 are determined by the resistors at the ton1 and ton2 pins respectively. there are two low-side drivers for the external power mosfets. both drivers are powered by the pvcc3 pin, which is normally connected to the output of vr1. the integrated amplifier has low offset and drift so, the mcu can accurately sense the amplified module current. overcurrent and overvoltage condit ions can be monitored by the two general purpose high-speed comparators. any detected fault condition can be used to trigger an mcu interrupt. the preload function is specially designed for solar applications. it applies a resistive load to the input power source to verify that it is sufficient for device operation. vr2, the mcu supply, will not be enabled until the input power source has enough power. this function can significantly reduce the power cycling of the mcu at system start-up and shutdown. the ISL1801 also includes a wa tchdog circuit to prevent the software in the mcu from hanging in an unknown state. the mcu can use the watchdog input (wdi) pin to periodically restart the timer. the watchdog timeout is se t by a resistor to vcc5v and a capacitor to ground, both connected to the timer pin. if the rc timer expires before an mcu re set on the wdi pin the pgood2 pin will be pulled low to reset the mcu. figure 17. ISL1801 simplified block diagram vin1 pwm1 l1 pv panel vout1 (10v) vcc1 ldo1 driver3 pwm3 bcmd mcu mcu power mosfet vin2 l2 vout2 (3.3v) vcc5v fb2 fb1 vth3 pgood2 mcu 0.88*vref2 opamp and comparators ISL1801 vr1 preload vout1 timer vcc5v pgood2 vth2 por enable vr1 enable vr2 bdriver power mosfet high speed driver pvcc3 pvcc3 ldo2 watchdog pre-load control mcu wdi pwm2 vr2 + + - - + - + - vcc 1 vcc 1 vcc5 v vcc5 v
ISL1801 17 fn8259.1 july 24, 2014 submit document feedback detailed operation dual synchronous buck switching regulators with constant on time control there are two synchronous buck switching regulators in the ISL1801. the high voltage switching regulator, vr1, can be connected to a power source up to 90v. the low voltage switching regulator, vr2, supports input voltages up to 14v. typically, vr2 is connected to the output of vr1. both switching regulators include integrated mosfets. both vr1 and vr2 employ a constant on time pwm control architecture with input voltage feed-forward. the constant on time pwm control architecture relies on the output ripple voltage to provide the pwm ramp signal; thus the output filter capacitor's esr acts as a current feedback resistor. for some applications with ceramic capacitors, the output voltage ripple is small due to very low esr. in order to achieve the stable operation for very low voltage ripple applications, one internal ramp is generated and added to the fb signal to emulate the output voltage ripple. the high-side switch on time is determined by a one-shot, which period is inversely proportional to input voltage and directly proportional to output voltage. another one-shot sets a minimum off time (300ns typical for vr1 and 150ns typical for vr2). the on time one-shot triggers when the following conditions are met; the error comparator's output is high, the synchronous rectifier current is below the current limit threshold, and the minimum off time one-shot has timed out. the controller utilizes the valley point of the output ripple to regulate and determine the off time. switching frequency of vr1 and vr2 each pwm core includes a one-shot that sets the on time for the high-side switch of each voltage regulator. each fast, low jitter, adjustable one-shot includes circui try that varies the on time in response to the input voltage and output voltage. this algorithm results in a nearly constant swit ching frequency despite the lack of a fixed-frequency clock generator. the high-side switch on time is inversely proportional to the input voltage as measured by the ton1 and ton2 pins for vr1 and vr2 respectively. both ton1 and ton2 pins are tied to an internal voltage reference and the current flowing into these pins is monitored to generate the on time one-shot. for high voltage vr1, the ton1 pin is tied to an internal 1v reference and the width of the on time one-shot is: v in1 is the input voltage for high voltage vr1, while r on1 is the resistor from v in1 to the ton1 pin. the switching frequency of vr1 is: when v in1 is much larger than 1v, the switching frequency of vr1 is almost independent of its input voltage: for a 10v output, the switching frequency of vr1 is about 370khz with r on1 = 1m . for low voltage vr2, the ton2 pin is tied to an internal 0.5v reference and the width of the on time one-shot is: v in2 is the input voltage for vr2, while r on2 is the resistor from v in2 to the ton2 pin. the switching frequency of vr2 is: when v in2 is much larger than 0.5v, the switching frequency of vr2 is almost independent of its input voltage: for a 3.3v output, the switchin g frequency of vr2 is about 314khz with r on2 = 1m . current limiting of vr1 and vr2 to prevent the output current fr om becoming too high, a new on time pulse can start only when the current through the synchronous mosfet is below the cu rrent limiting threshold. this limits the valley of the output inductor current to a fixed value, typically 140ma for vr1 and 200ma for vr2. the maximum peak current throug h the output inductor is the sum of the current limiting th reshold and the current ripple determined by the on time, indu ctor value and the input/output voltage. diode emulation operation to improve the efficiency for light loads, the synchronous mosfet is turned off when its current drops to 0. this prevents negative current through the ou tput inductor emulating diode operation. with diode emulation operation un der light load conditions, the output voltage may drop slowly after the synchronous mosfet turns off. it may take a long time for the output voltage to drop below the reference voltage to start a new switching cycle. this will have the effect of reducing the switching frequency under light load conditions. (eq. 1) t on1 2.7e 11 ? r on1 ? v in1 1 ? ----------------------------------------- = (eq. 2) f sw1 v out1 v in1 1 ? ?? ? 2.7e 11 ? r on1 v in1 ?? ---------------------------------------------------------- - = (eq. 3) f sw1 v out1 2.7e 11 ? r on1 ? ----------------------------------------- ? t on1 1.05e 11 ? r on2 ? v in2 0.5 ? -------------------------------------------- - = (eq. 5) f sw2 v out2 v in2 0.5 ? ?? ? 1.05e 11 ? r on2 v in2 ?? -------------------------------------------------------------- = (eq. 6) f sw2 v out2 1.05e 11 ? r on2 ? -------------------------------------------- - ?
ISL1801 18 fn8259.1 july 24, 2014 submit document feedback overvoltage protection the feedback voltage for vr1 and vr2 is continuously monitored to prevent the output voltage from going too high. when the vr1 output voltage feedback fb1 is higher than 120% of vref1, the overvoltage protection (ovp) is triggered. when this condition occurs, the lower-side mosfet of vr1 is turned on immediately. at the same time, the preload current will be applied to v out1 to discharge the output. when the current through the lower side mosfet drop s to 0, turn off this mosfet to prevent the negative inductor current. the ovp is reset when fb1 voltage drops to vref1. for low voltage vr2, ovp is triggered when the fb2 voltage is above 0.775v. when this condition occurs, the lower synchronous mosfet of vr2 is turn ed on immediately. it is held on until the fb2 voltage drops below 0.73v. power-good signal (pgood2) both vr1 and vr2 have their own power-good signals to indicate that their output voltage is within the regulation window. only the vr2 power-good signal is externally available at the pgood2 pin. vr1?s power-good signal is used in ternally and is not available on an external pin. the pgood2 pin is a true open drain output. the power-good comparator continuously monitors the feedback voltage fb2 for an undervoltage condition. pgood2 is active low during shutdown or when fb2 is below the threshold voltage. when the fb2 voltage goes above 88% of its reference voltage (0.88 * 0.73v = 0.64v), pgood2 is released and the pin will be a high impedance. the pgood2 signal can be used to reset the mcu powered by the output of vr2. the watchdog timer will also pull pgood2 low when a timeout occurs. please refer to ? watchdog timer ? on page 20 for more information. dual ldo bias supplies there are two ldos in the ISL1801 to manage start-up and power internal control circuitry. the high voltage ldo1 can be dire ctly connected to an input power source up to 90v. its output is connected to the vcc1 pin and is typically about 6.7v. vcc1 provides the bias voltage for the power stage of high voltage regulator. typically, the vcc1 pin should be connected to v out1 , the output of high voltage regulator vr1. before vr1 starts to operate, ldo1 can charge up the capacitor at vcc1 when it is tied to v out1 . when the v out1 /vcc1 voltage reaches 6.5v, vr1 starts to operate and will ramp v out1 /vcc1 to a higher voltage. once the vcc1 voltage is above 6.7v, ldo1 is disabled. ldo1 limits its output current to 10ma. there is a second low voltage ldo2 which can be connected to inputs up to 14v. ldo2?s 5v output is connected to the vcc5v pin. typically, ldo2 is connected to the input voltage of low voltage vr2 (typically v out1 ). ldo2 supplies power for internal circuitry such as the current sense op amp, logic circuits, comparators and the vr2 control circuits. one 2.2f capacitor is recommended at the vcc5v pin. ldo2 limits its output current to 10ma. dual low-side mosfet drivers the ISL1801 has two low-side drivers for power mosfets connected to the drive3 and bdrive pins. their high output current enables them to rapidly charge and discharge the gate capacitance of power mosfets. both drivers are powered by the pvcc3 pin, and each driver has its own ground pin. pgnd3 is the ground connection for drive3 and pgnd4 is the ground connection for bdrive. the gate drivers (drive3 and bdrive) are always pull-down to ground by internal 14k resistor. additional 250 pull-down resistor is available only after the 5v ldo vcc5v has come up higher than 3.2v. drive3 control logic drive3 is controlled by the pwm3 signal. when pwm3 = 1, the drive3 output is connected to pvcc3 by its upper switch. when pwm3 = 0, drive3 is connected to pgnd3 through its lower switch. however there are other logic signals which influence the state of drive3. before power on reset (por) drive3 is forced low. when the output of comparator 1 (cmp1o ) or comparator 2 (cmp2o) is high it triggers a flip-flop (ff1) setting the open drain latch report (latchrpt) signal low. it also connects drive3 to pgnd3 immediately. the rpwm3 pin has to be forced low to reset this condition. since the set input of flip-flop ff1 overrides the reset input, drive3 is always held low when cmp1o or cmp2o is high even when rpwm3 = 0. drive3 overcurrent limiting a comparator monitors the phase3 voltage when drive3 is high to detect a possible overcurrent co ndition. when this comparator output is high, drive3 is immediately connected to pgnd3. this action provides overcurrent prot ection (ocp) for the power stage driven by drive3. figure 18 shows the block diagram of the phase3 ocp function. the phase3 overcurrent limiting level is defined by the ocset3 pin. a 120a current is supplied by the ocset3 pin. placing a resistor from the ocset3 pin to pgnd3 sets the overcurrent threshold voltage. a capacitor may be placed in parallel with the ocset3 resistor to filter noise and provide a more consistent ocp threshold. when drive3 = 1, the internal swit ch s3 is turned on feeding the phase3 signal to the ocp comparator. the phase3 voltage is equal to the product of the current i1 and the conduction resistance r ds(on) of the power mosfet q1. when the phase3 pin voltage is higher than the ocset3 pin voltage, the drive3 ocp is triggered. the overcurrent limiting level is: (eq. 7) i oc3 120 ? ar1 ? r ds on ?? ------------------------------ - =
ISL1801 19 fn8259.1 july 24, 2014 submit document feedback once the overcurrent protection is triggered flip-flop ff2 is set forcing drive3 low. rpwm3 or pwm3 must be pulled low to reset an ocp event. since the set input of flip-flop ff2 overrides the reset input, drive3 is always held low in an overcurrent condition even if rwpm3 = 0. the ocp flip-flop output also triggers a one-shot block to generate a narrow pulse sett ing latchrpt low for 1s. for normal operation an ocp event terminates the drive3 on state early by forcing drive3 to pgnd3. the ocp event is reset by setting pwm3 = 0. this allows drive3 to be turned on by the following pwm3 = 1 pulse. however, special attention is needed for long-term or continuous ocp operation. if the ocp is continuously triggered with rpwm3 = 0 and pwm3 = 1, then a very high switching frequency may occur on the drive3 pin. referring to figure 18 the following sequence of events will lead to this oscillation. when i1 is larger than the preset ocp level, it may trigger ocp immediately when drive3 = 1. once ocp is triggered, drive3 is pulled low, and s3 is turned off setting the oc p comparator output low. since rpwm3 = 0, the flip-flop ff2 is reset immediately. however, the 1s one-shot will keep latchrpt low for at least 1s forcing the drive3 pin low for at least 1s. after 1s drive3 is forced high resulting in another ocp. this operation re peats until pwm3 = 0, rpwm3 = 1 or i1 drops below the ocp threshold. this condition may result in a 100khz switching frequency at drive3. bdrive control logic the bdrive pin is controlled by the bcmd signal. when bcmd = 1, the bdrive output is connected to pvcc3 by its upper switch. when bcmd = 0 the bdrive pin is connected to pgnd4 through its lower switch. when any fault condition occurs, the latchrpt signal is set low. it will also set flip-flop ff3 and connect the bdrive pin to pgnd4 until flip-flop ff3 is reset by setting breset = 1. bdrive is held at pgnd4 prior to por. the bdrive logic is shown in figure 19 . when vddref is not applied during the start, the output of the level shift block is undefined. in order to prevent bdrive turning on by mistake, it?s recommended adding some offset (~50mv) on vddref pin to make the por and gate output low. dual high-speed comparator the ISL1801 has two high-speed co mparators for fault detection. the output of either comparator can set the flip-flop ff1 to indicate a fault at the open-drain latchrpt pin. the fault can be cleared by setting rpwm3 = 0 to reset flip-flop ff1. the two comparators are identical but only the output of comparator 1 (cmp1) is available at the cmp1o pin. cmp1o is a push-pull output and its output high level is clamped to vddref. the fault detection logic is shown in figure 20 . drive3 ocset pgnd3 ISL1801 r1 c1 q1 i1 phase3 pgnd3 s3 q q set clr s r pvcc3 por 120a on shot latchrpt rpwm3 pwm3 q q set clr s r cmp1o cmp2o ff1 ff2 figure 18. low-side driver logic figure 19. bdrive control logic figure 20. fault detection logic rpwm3 cmp1o cmp1- cmp1+ cmp2- cmp2 cmp1 latchrpt cmp2+ ocp3 q q set clr s r one shot ISL1801 ff1 vddref
ISL1801 20 fn8259.1 july 24, 2014 submit document feedback precision amplifier the ISL1801 includes a precision amplifier for current sensing. this low offset and low temperature drift op amp can be used to accurately amplify the voltage drop across a known shunt resistor to provide a current measurement for the mcu. due to the very low amplitude input signal, it is necessary to include some capacitance as a noise filter . the typical application circuit is shown in figure 21 . the current sense gain is set by the ratio of r1/r2. capacitor c1 implements a low-pass filter to reduce high frequency noise effectively averaging the desired signal. c2 is optional and can provide additional noise filtering if required. . preload operation during morning start-up, shading events or evening shutdown, pv modules may not provide enough output power to run the micro converter. when this happens it may result in a repetitive voltage dropout at the vr2 output. when the vr2 output powers the mcu, this may cause a system reset after each dropout. the repetitive restart operation of mcu may impact on the system reliability. to avoid this issue, the ISL1801 includes the preload feature to test the power source before enabli ng vr2. this test is performed by gradually applying a preload current to the output of vr1/v out1 . if the preloaded vr1 output voltage drops below the preset threshold, the preload is removed immediately. after the vr1 output voltage recovers, the pr eload test is repeated. if vr1 can support the preload current and maintain its output voltage above the preset threshold for some time the input power source has enough power for the system operation. the preload is then removed, and vr2 is enabled and will perform a soft-start. figure 22 shows the ISL1801s preload circuit. the four mosfets each have a different on resistan ce that can be connected to the preload pin. this allows the ISL1801 to increase the preload current step-by-step, as shown in figure 23 . when the preload is enabled, q1 turns on for about 500s. during this time the current applied to the vr1 output as shown by equations:: next, q2 turns on with q1 and the preload current becomes: next, q3 turns on with q1 and q2; finally all the mosfets are on resulting in the minimum resist ance from the preload pin to gnd: after all the mosfet switches are on the timer pin is pulled to gnd for 1ms and then released to ramp-up. if the vr1 output voltage stays above the preset threshold until the timer pin ramps to 90% of vcc5v, the preload is removed step-by-step, as shown in figure 23 . if the vr1 output drops belo w the preset threshold all the switches are turned off immediately. the ? power-up sequence ? on page 22 provides additional details. watchdog timer the watchdog timer circuit in figure 24 verifies correct mcu operation by monitoring the wdi input pin. the mcu must periodically toggle the wdi pin to prevent a timeout. if a timeout occurs, the pgood2 pin will be pulsed low for 0.5ms providing a signal that can reset the mcu. pgood2 will then remain high until the next timeout or invalid voltage event. the timeout interval is determined by the capacitor and resistor connected to the timer pin. any low-to-high or high-to-low transition on the wdi pin forces the timer pin low for 1.5ms to discharge the capacitor from the timer pin to ground. after the 1.5ms period the timer pin is rele ased so the resistor can start charging the capacitor. when the timer pin voltage reaches 90% of the vcc5v supply voltage a time-out event is triggered. figure 21. precision current sense amplifier amp- amp+ ampo vddref pgnd + - + - c1 c2 c1 r1 r1 r2 r2 rs i sense (eq. 8) i vr1 v vr1 r pl r ds on ?? 1 + ------------------------------------------- = (eq. 9) i vr1 v vr1 r pl r ds on ?? 1 r ds on ?? 2 ?? ?? + ------------------------------------------------------------------------------- - = (eq. 10) i vr1 v vr1 r pl r ds on ?? 1 r ds on ?? 2 r ds on ?? 3 r ds on ?? 4 ?? ?? ?? ?? + ------------------------------------------------------------------------------------------------------------------------------- ---------------- = figure 22. preload switches preload vr1 output q 4 q 3 q 2 q 1 r_pl ISL1801 350 120 50 12 r ds(on)1 r ds(on)2 r ds(on)3 r ds(on)4 q1 on off t 1 t 2 t 3 t 4 t 0 t 5 t 6 t 7 q2 on off q3 on off q4 on off off off off off enable figure 23. preload timing diagram
ISL1801 21 fn8259.1 july 24, 2014 submit document feedback the wdi pin is pulled to vddref by an internal 40k resistor. when the wdi pin is floating, the wdi voltage will be vddref. the wdi signal is compared to two threshold voltages resulting in the periodic discharge of the capacitor on the timer pin or disabling the watchdog function. the wdi pin voltage is compared to vddref/2 to determine if there is any activity on the pin. an y rising or falling transition on the wdi pin that crosses the vddr ef/2 threshold will generate a one-shot pulse to pull the timer pin low for 1.5ms. the wdi pin voltage is also compared to 90% of vcc5v. if the wdi pin is above 90% of vdd5v the watchdog feature will be disabled and the timer capacitor will not be discharged. if the wdi pin voltage stays at any constant voltage below the disable threshold the resistor fr om timer to vcc5v will charge the capacitor. when the timer pin voltage reaches 90% of vcc5v a time-out event is triggered and pgood2 will be set low for 0.5ms. whenever wdi enters or exits its disable mode the timer pin is pulled low for 1.5ms. it is important to note that the maximum leakage current into the timer pin is 1a. this le akage current across the pull-up resistor will set the maximum volt age on the timer pin. in order to assure correct operation, the pull-up resistor from the timer pin to vcc5v should never be more than 200k . the voltage drop for 1a across 200k is 200mv, well be low the 90% threshold value of 5v - (5v * 90%) or 5v - 4.5v = 500mv. this is important because soft-start is initiated by crossing the 90% of vdd5v threshold and the watchdog time out also depends on crossing this threshold. figure 25 shows the typical operational waveforms of the watch-dog timer circuit. t 0 :the vr1/v out1 voltage ramps up to its threshold voltage; wdi is pulled to vddref, which is 0v; timer starts to ramp-up. t 1 : timer reaches the 90% thresh old (0.9 * 5v = 4.5v) and starts to initialize the ISL1801. t 2 : all preloads are sequentially applied, reset timer and hold it low for 1.5ms. t 3 : 1.5ms timeout, timer starts to ramp up. t 4 : timer voltage reaches 90% thre shold, release all preloads and enable vr2 soft-start. t 5 : vr2 finishes soft-start and pgood2 goes high; reset timer and hold for 1.5ms, then enable the watchdog function; mcu starts to run, wdi is floating at vddref, timer ramps up. t 6 : mcu sends out the first pulse and the wdi falling edge (from high to low) resets timer for 1.5ms; then timer ramps up. t 7 : timer is reset for 1.5ms by the wdi rising edge; then timer ramps up. t 8 : timer is reset for 1.5ms by the wdi falling edge; then timer ramps up. t 9 : timer is not reset in time and reaches 90% threshold level; pgood2 is pulled low for 1ms to reset mcu; and timer is reset for 1.5ms. t 10 : pgood2 goes back high to exit mcu reset. t 11 : 1.5ms timeout, timer ramps up. t 12 : timer is reset for 1.5ms by the wdi rising edge; then timer ramps up. t 13 : timer is not reset in time and reaches the 90% threshold level; pgood2 is pulled low for 1ms to reset mcu; and timer is reset for 1.5ms. t 14 : pgood2 goes back high to exit mcu reset; then timer ramps up. figure 24. watchdog timer logic wdi vddref 40k r r ISL1801 one shot timer en 0.9*vcc5v 0.9*vcc5v vcc5v time-out wdi timer pgood2 t 1 t 2 t 3 t 4 t 0 v out1 t 5 t 6 t 7 t 11 t 10 t 9 t 8 t 13 t 12 t 14 t 16 t 15 t 17 t 19 t 18 4.5v 4.5v 0.6*vddref t 20 figure 25. watchdog timer waveforms
ISL1801 22 fn8259.1 july 24, 2014 submit document feedback t 15 : wdi voltage changes from vddref to 0.6*vddref; since it does not cross the vddref/2 threshold no falling edge signal is generated; ti mer continues ramping up. t 16 : timer is not reset in time, and reaches the 90% threshold level; pgood2 is pulled low for 1ms to reset mcu; and timer is reset for 1.5ms. t 17 : pgood2 goes back high to exit mcu reset; then timer ramps up. t 18 : timer is reset for 1.5ms by the wdi falling edge; then timer ramps up. t 19 : timer is reset by the wdi rising edge; wdi is above 90%*vcc5v threshold level, watchdog function is disabled. timer ramps up and stays at its high state however it does not trigger a time-out. t 20 : wdi drops below the 90%*vcc5v threshold level, watch-dog function is enabled; timer is reset for 1.5ms by the wdi falling edge; then timer ramps up. power-up sequence before t 0 , the pv module does not output any voltage t 0 : panel output voltage v in1 starts to ramp up; ldo1 is on to pull v out1 (=pvcc3) up; ldo2 runs in saturated condition to pull vcc5v up. t 1 : when vcc5v reaches its power on reset (por) level (4.5v), the ISL1801 starts to operate and monitor the voltage at the timer pin; after timer reaches its threshold (90% * vcc5), the ISL1801 starts to initialize all internal circuits; then vr1 starts to run at the maximum du ty cycle, and the vr1 current limiting level starts to ramp up step-by-step; ldo1 continues to output some current until pvcc3 reaches about 6.2v. t 2 : vr1 current limiting level ramps up to its final value. t 3 : fb1 reaches v th3 (90% of its final value), the preload switches are turned on in sequence to apply the preload current to the vr1 output. t 4 : if the pv module does not have sufficient output power, pvcc3 will drop to v th2 (fixed at 7v) when the preload is applied; this triggers the immediate removal of all preload current followed by a 500s delay. figure 26. power-up sequence fb1 pvcc3 vin1 pwm2 vout2 pgood2 preload current off vcc5v por opamp, comparators, driver3, bdrive enabled pwm1 timer pwm3 disabled 4.5v v th3 t 1 t 2 t 3 t 4 v th2 t 0 t 5 t 6 t 7 on vr1 current limiting level on t 9 t 10 t 8 4.5v
ISL1801 23 fn8259.1 july 24, 2014 submit document feedback t 5 :when pvcc3 goes above v th2 again, slowly apply the preload current to vr1 output. t 6 : if pvcc3 stays above v th2 after the maximum preload current is applied the timer voltage is pulled to 0v for 1.5ms and released; the external r-c causes the timer pin voltage to ramp up. t 7 : timer voltage reaches its 90% threshold; starts to remove preload step-by-step; from now on, pvcc3 and fb1 are not monitored for shut-down. only vcc5v is monitored for undervoltage lock out (uvlo). t 8 : preload is removed; vr2 starts to ramp up. t 9 : fb2 reaches 90% of its final value; pgood2 open-drain switch is open to allow pgood2 to rise. t 10 : pgood2 is high; all internal circuits, including driver, opamp and comparators are enabled. note: vr1 current limiting level will ramp up step-by-step with a 25% increase for each step. the preload will be applied only after the vr1 current limiting level reaches its final value and fb1 is above v th3. power-down sequence before t 0 , the system runs in normal mode: t 0 : pvcc3 drops below v th2 , both drivers? outputs are pulled to gnd; mcu should stop sending pwm signal; both vr1 and vr2 continue operating. t 1 : pvcc3 returns above v th2 , both drivers are ready to run. t 2 : pvcc3 drops below v th2 , both drivers? outputs are pulled to gnd; both vr1 and vr2 continue operating. t 3 : pvcc3 drops to a very low level and vcc5v drops below the por level (4.5v); the ic shuts down and all internal circuits are disabled. when vcc1 drops below 6v, the vr1 power stage stops operating. the vr1 control circuit will still run until vcc5v drops below the 90% * vcc5 (4.5v) por threshold. figure 27. power-down sequence pvcc3 vin1 pwm2 vout2 pgood2 pre_load off ldo2 on off vcc5v opamp, comparator enabled pwm1 timer driver3/ bdrive enabled disabled pwm3 disabled v th2 t 1 t 2 t 3 t 0 por 4.5v gnd gnd
ISL1801 24 fn8259.1 july 24, 2014 submit document feedback over-temperature protection over-temperature protection (otp) is placed on the hv die. temperature higher than +150c (typ ical) will trip the otp disabling vr1, vr2 and the mosfet driv ers. when the temperature decreases to +135c (typical), the ISL1801 will restart. overvoltage protection vr1 and vr2 include overvoltage protection (ovp): when the vr1 output voltage feedback is higher than 120% of v ref1 , the pwm output will be tri-stated and at the same time the preload current will be applied to v out1 to discharge the output. when v out1 is discharged and fb1 reaches v ref1 the ocp will turn off and normal pwm operation will resume. when the vr2 output voltage feedback is higher than 120% of v ref2 , the pwm output will be tri-stated. after v out2 falls so that fb2 is equal to v ref2 the ocp will turn off and normal pwm operation will resume. applications information application circuits figure 28. boost regulator pv panel q1 rs vout+ inverter / load isen+ isen- nc3 phase3 pgnd3 drive3 pvcc3 pwm3 wdi vddref latchrpt pgood2 breset rpwm3 bcmd cmp1o fb2 boot2 boot1 timer ton1 fb1 cmp2+ pgnd2 cmp2- phase2 vin2 vcc5v cmp1- phase1 ampo amp- amp+ gnd bdrive ton2 preload 6 7 8 9 10 12 17 18 19 20 21 13 16 14 15 22 23 24 11 43 42 41 40 39 37 32 31 30 29 28 36 33 35 34 27 26 25 38 ISL1801 isen- isen+ vin+ vin- gnd vout- pgnd4 3.3v 10v vin+ vout2 vout1 vout2 sgnd nc1 nc2 vcc1 agnd ocset3 pgnd1 nc5 vin1 nc4 nc6 1 2 3 4 5 48 47 46 45 44 cmp1+ vout2 vout2 mcu vout1 vcc5v lo
ISL1801 25 fn8259.1 july 24, 2014 submit document feedback figure 29. fly back regulator application circuits (continued) pv panel rs isen+ isen- nc3 phase3 pgnd3 drive3 pvcc3 pwm3 wdi vddref latchrpt pgood2 breset rpwm3 bcmd cmp1o fb2 boot2 boot1 timer ton1 fb1 cmp2+ pgnd2 cmp2- phase2 vin2 vcc5v cmp1- phase1 ampo amp- amp+ gnd bdrive ton2 preload 6 7 8 9 10 12 17 18 19 20 21 13 16 14 15 22 23 24 11 43 42 41 40 39 37 32 31 30 29 28 36 33 35 34 27 26 25 38 ISL1801 isen- isen+ vin+ vin- pgnd4 3.3v 10v vin+ vout2 vout1 vout2 sgnd nc1 nc2 vcc1 agnd ocset3 pgnd1 nc5 vin1 nc4 nc6 1 2 3 4 5 48 47 46 45 44 cmp1+ vout2 vout2 mcu vout1 vcc5v q1 load
ISL1801 26 fn8259.1 july 24, 2014 submit document feedback figure 30. synchronous buck regulator with external half bridge driver application circuits (continued) pv panel rs isen+ isen- nc3 phase3 pgnd3 drive3 pvcc3 pwm3 wdi vddref latchrpt pgood2 breset rpwm3 bcmd cmp1o fb2 boot2 boot1 timer ton1 fb1 cmp2+ pgnd2 cmp2- phase2 vin2 vcc5v cmp1- phase1 ampo amp- amp+ gnd bdrive ton2 preload 6 7 8 9 10 12 17 18 19 20 21 13 16 14 15 22 23 24 11 43 42 41 40 39 37 32 31 30 29 28 36 33 35 34 27 26 25 38 ISL1801 isen- isen+ vin+ vin- pgnd4 3.3v 10v vin+ vout2 vout1 vout2 sgnd nc1 nc2 vcc1 agnd ocset3 pgnd1 nc5 vin1 nc4 nc6 1 2 3 4 5 48 47 46 45 44 cmp1+ vout2 vout2 mcu vout1 vcc5v isl2110 q1 q2 lo half bridge driver hi li ho lo vout+ load
ISL1801 27 fn8259.1 july 24, 2014 submit document feedback pc board layout guidelines careful pc board layout is critical to achieve minimal switching losses and clean, stable operation. this is especially true when multiple converters are on the same pc board where one circuit can affect the other. for specific layout example of the ISL1801eval1za evaluation board please contact intersil sales support with your needs. mount all of the power components on the top side of the board with their ground terminals flush against one another, if possible. follow these guidelines for good pc board layout: ? isolate the power components on the top side from the sensitive analog components on the bottom side with a ground shield. use a separate pgnd plane under the v out1 and v out2 sections (called pgnd1 and pgnd2). avoid the introduction of ac currents into the pgnd1 and pgnd2 ground planes. run the power plane ground currents on the top side only, if possible. ? use a star ground connection on the power plane to minimize the crosstalk between v out1 and v out2 . ? keep the high-current paths short, especially at the ground terminals. this practice is essential for stable, jitter-free operation. ? keep the power traces and load connections short. this practice is essential for high efficiency . using thick copper pc boards (2oz vs 1oz) can enha nce full-load efficiency by 1% or more. correctly routing pc board traces must be approached in terms of fractions of centimeters, where a single mw of excess trace resistance causes a measurable efficiency penalty. ? phase3 and gnd connections to the synchronous rectifiers for current limiting must be made using kelvin-sense connections to guarantee the current-limit accuracy. this is best done by routing power to the mosfets from outside using the top copper layer, while connecting phase traces inside (underneath) the mosfets. ? when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging pa th to be made longer than the figure 31. buck-boost regulator with external half bridge drivers application circuits (continued) isen- isl2110 q1 q2 lo half bridge driver hi li ho lo isl2110 q3 q4 half bridge driver ho lo hi li vout+ load nc3 phase3 pgnd3 drive3 pvcc3 pwm3 wdi vddref latchrpt pgood2 breset rpwm3 bcmd cmp1o fb2 boot2 boot1 timer ton1 fb1 cmp2+ pgnd2 cmp2- phase2 vin2 vcc5v cmp1- phase1 ampo amp- amp+ gnd bdrive ton2 preload 6 7 8 9 10 12 17 18 19 20 21 13 16 14 15 22 23 24 11 43 42 41 40 39 37 32 31 30 29 28 36 33 35 34 27 26 25 38 ISL1801 isen- isen+ pgnd4 3.3v 10v vin+ vout2 vout1 vout2 sgnd nc1 nc2 vcc1 agnd ocset3 pgnd1 nc5 vin1 nc4 nc6 1 2 3 4 5 48 47 46 45 44 cmp1+ vout2 vout2 mcu vout1 vcc5v pv panel rs isen+ isen- vin+ vin-
ISL1801 28 fn8259.1 july 24, 2014 submit document feedback discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the synchronous rectifier or betwee n the inductor and the output filter capacitor. ? ensure that the out connection to cout is short and direct. however, in some cases it may be desirable to deliberately introduce some trace length be tween the out connector node and the output filter capacitor. ? route high-speed switching nodes (boot, phase, drive3 and bdrive) away from sensitive an alog areas (vddref, fb and amp). use pgnd1 and pgnd2 as an emi shield to keep radiated switching noise away from the ic's feedback divider and analog bypass capacitors. ? make all pin-strap control input connections to gnd or vcc of the device. layout procedure place the power components fi rst with ground terminals adjacent. if possible, make all these connections on the top layer with wide, copper-filled areas. mount the controller ic adjacent to the synchronous rectifier mosfets close to the hottest spot, preferably on the back side in order to keep drive3, gnd, and the bdrive gate drive lines short and wide. the drive3 gate trace must be short and wide, measuring 50 mils to 100 mils wide if the mosfet is 1? from the controller device. group the gate-drive components (boot capacitor, vin bypass capacitor) together near the controller device. make the dc/dc controller ground connections as follows: 1. near the device, create a small analog ground plane. 2. connect the small analog ground plane to gnd and use the plane for the ground connection for the vddref and vcc bypass capacitors, fb dividers and ilim resistors (if any). 3. create another small ground island for pgnd and use the plane for the vin bypass capacitor, placed very close to the device. 4. connect the gnd and pgnd pl anes together under device. on the board's top-side (power planes), make a star ground to minimize crosstalk between the two sides. the top-side star ground is a star connection of the input capacitors and synchronous rectifiers. keep the resistance low between the star ground and the source of the sync hronous rectifiers for accurate current limit. connect the top-side star ground (used for mosfet, input, and output capacitors) to the small island with a single short, wide connection (preferably just a via). create pgnd islands on the layer just below the top-side layer to act as an emi shield if multiple layers are available (highly recommended). connect each of these individually to the star ground via, which connects the top-side to the pg nd plane. add one more solid ground plane under the device to act as an additional shield, and also connect the solid ground plane to the star ground via. connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias.
ISL1801 29 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8259.1 july 24, 2014 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change july 24, 2014 fn8259.1 ? absolute maximum ratings ? on page 7 : changed bdrive, drive3 voltages from: -0.3v to vcc1+0.3v bdrive, to:-0.3v to pvcc3+0.3v. updated description of pin vcc1 on page 4 . updated electrical spec tables. june 29, 2012 fn8259.0 initial release.
ISL1801 30 fn8259.1 july 24, 2014 submit document feedback package outline drawing m48.240 48 lead thin shrink small outline package (tssop) rev 1, 11/10 top view bottom view detail "a" side view typical recommended land pattern 48 pin 1 id b a c 0.20 m 0.08 5 0.50 6.10.10 8.1 0.17-0.27 4 2x n/2 tips 3 2 1 b b a c 0.09-0.20 see detail "a" c l 12.500.10 0.05/0.15 4 0.900.05 seating plane 0.10 0.05 c c 3 0.25 h 0.60.15 line (12) typ (1.00) (0-8) (1.45) (46x 0.50) (48x 0.28) (7.35) notes: 1. all dimensions are in millimeters (angles in degrees). 2. dimensioning & tolerances per asme. y14.5m-1994. 3. datum plane h located at mold parting line and coincident with lead where lead exits plastic body at bottom of parting line. 4. at reference datum and does not include mold flash or protrusions, and is measured at the bottom parting line. mold flash or protrusions shall not exceed 0.15mm on the package ends and 0.25mm between 5. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of 6. this part is compliant with jedec specification mo-153 variation the leads. the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and an adjacent lead should be 0.07mm. ed except it is 0.1mm thinner. 7. dimensions in ( ) are for reference only. scale: (none) (view rotated 90 c.w.) parting 1.10 max a

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